Greetings from Canvendor!
Role:
ASIC Design Lead
Location:
Bangalore
Notice period:
30days
Key Responsibilities:
- 8-13years experience in ASIC design & integration
- Experience in leading the design and development of SOC/RTL teams from RTL to GDSII
- Collaborate with architecture, verification, DFT, PD, software, and silicon validation teams to define design specifications and requirements
- Develop and implement RTL designs using Verilog, VHDL, or System Verilog.
- Experience & knowledge of RTL quality checks & LINT, CDC, RDC tools
- Conduct design reviews, provide technical guidance, and mentor junior engineers
- Work closely with verification, DFT, PD teams to ensure thorough Verification of designs
- Debug and resolve design issues, ensuring robust and reliable designs
- Manage project schedules, deliverables, and resources to ensure timely completion of design projects.
If interested Candidate kindly share your updated resume to