Design and development of Instruction Sequencing Unit for high-performance Processor CPU of IBM Systems.- Architect and design Instruction Dispatch to Issue queues, Register Renaming for Out of Order Execution, Issue instructions to Execution Pipelines, Reordering Buffers for completion of a high performance processor CPU- Develop the features, present the proposed architecture in the High leveldesign discussions- Estimate the overall effort to develop the feature.- Estimate silicon area and wire usage for the feature.- Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature- Signoff the Pre-silicon Design that meets all the functional, area and timing goals- Participate in post silicon lab bring-up and validation of the hardware- Lead a team of engineers, guide and mentor team members, represent a Design and development of Instruction Sequencing Unit for high-performance Processor CPU of IBM Systems.- Architect and design Instruction Dispatch to Issue queues, Register Renaming for Out of Order Execution, Issue instructions to Execution Pipelines, Reordering Buffers for completion of a high performance processor CPU- Develop the features, present the proposed architecture in the High leveldesign discussions- Estimate the overall effort to develop the feature.- Estimate silicon area and wire usage for the feature.- Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature- Signoff the Pre-silicon Design that meets all the functional, area and timing goals- Participate in post silicon lab bring-up and validation of the hardware- Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums.