Technical Skills:
- 15+ Years of experience.
- As a Design-for-Testability (DFT) Architect, the candidate is expected to have prior experience in defining the DFT Architecture, methodology flow and DFT implementation verification plan.
- The candidate also should have DFT end to end execution experience from DFT spec definition to post silicon bringup.
- The candidate will meet regularly with other functional team members such as Architects, Verification Engineers, Physical Designers, CAD Engineers, So C Design Engineers, Product Engineers and Program Management to ensure successful and timely project completion.
- BTech/MTech/Ph D.
- DFT methodology/architecture and DFT verification experience (eg. IEEE1500, JTAG 1149. X, scan, memory BIST, PHY loopback, etc).
- Siemens Tessent and/or Cadence Modus.
- Experience with VCS simulation tool, Perl/Shell scripting and Verilog RTL design.
- Prior experience and exposure to DFT timing closure is critical.
- Pre-Silicon test planning & validation, engagement with design teams.
- Characterization and debug of Scan/ATPG test in the new silicon designs and process technologies.
- Optimization of test flows for increased quality and cost improvement.
- Analysis of part failures leading to test coverage and yield improvement.
- Analysis of characterization data across PVT.
- Must have good communication skills and the ability to work in a worldwide team environment.