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Memory Layout

India, Republic Of India, Bengaluru
Last update 2025-02-09
Expires 2025-03-09
ID #2566589484
Free
Memory Layout
India, Republic Of India, Bengaluru,
Modified January 24, 2025

Description

Job Description

  • Hands-on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array, decoders, etc in compiler context.
  • Hands-on experience with top-level memory integration and DRC, LVS, Density verification, and cleaning physicals across the compiler space.
  • Good handle on IR/EM-related issues in memory layouts.
    - Must have worked on cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks.
  • Strong knowledge of ultra-deep sub-micron layout design-related challenges and a good understanding of DFM guidelines.
  • Experience or strong interest in memory compilers developed.
  • Exp level:
    3-6 years
  • Technolgy nodes :
    tsmc 3nm,5nm

Job details:

Job type: Full time
Contract type: Permanent
Salary type: Monthly
Occupation: Memory layout

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