Job Description
- Hands-on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array, decoders, etc in compiler context.
- Hands-on experience with top-level memory integration and DRC, LVS, Density verification, and cleaning physicals across the compiler space.
- Good handle on IR/EM-related issues in memory layouts.
- Must have worked on cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks. - Strong knowledge of ultra-deep sub-micron layout design-related challenges and a good understanding of DFM guidelines.
- Experience or strong interest in memory compilers developed.
- Exp level:
3-6 years - Technolgy nodes :
tsmc 3nm,5nm