Published on May 10, 2025. Modified on May 12, 2025.
Job Description:
1. 3-6 years of experience in IO PHY / SERDES IP Design e.g. UCIe, HBMIO, DDRIO, PCIe, HDMI, USB etc., doing blocks like Transmitter, Receiver, PLL, Clocking blocks, DCC, Equalizers (FFE, CTLE, DFE) etc.
2. Should be proficient in Virtuoso and in setting up circuit Testbenches – circuit biasing, power noise simulations, stability analysis, Jitter Analysis, Power Up/down simulations, other performance simulations.
3. Should have strong Analog circuit fundamentals.
4. Expertise in scripting or.lib / Verilog modelling will be considered a big plus.
5. There are 3 open position for this requirement.
Interested please share your updated resume to janagaradha.n@acldigital.com
