RTL DESIGN (SCRIPTING)
Location:
Bengaluru
Experience Level:
5+ years
Job Responsibilities:
o The main task is to take an existing RTL configurator tool written in Python (RTL parser) and import it to Magillem 5 Connectivity - Arteris is a plus.
o Expertise in Verilog, Python and scripting in general.
o Exposure to Design For Test;
understanding of scan concepts and writing DFT
o Experience with DDR PHY design and mixed-signal environments
o Write high-quality RTL code (System Verilog) to describe the digital logic for complex systems.
o Implement and optimize digital systems including datapaths, control units, and interface logic.
o Create reusable modules and libraries to improve design efficiency. Write RTL code (Verilog) to describe the digital logic for complex systems.
Please share you resume to
Best Regards,
Puja Saha
Talent Acquisition - Hardware Engineering
Mirafra Software Technologies Pvt Ltd . Akshay Tech Park, Whitefield, Bangalore – 560066. India.
Email:
|Cell #:
+91 8637807369 |
** Mirafra has been awarded as the "Best company to work for – 2016" and "Most Promising Design Services Provider - 2018" by Silicon India **