LTTS is hiring for Physical Design Engineers with 5+ Years of experience. Job Location : Bangalore, India Job description is as below :: Top 5 Required Skills/Mandatory skills
1. Synthesis
2. Constraints Management
3. Logic Equivalence Check
4. CLP
5. STA
Required Education: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering or Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering
Key Words: Synthesis, Conformal, Formality, CLP, STA
Roles & Responsibilities:
RTL Synthesis to achieve the best Performance/Power/Area of the designs
DFT insertions that include MBIST and SCAN, setup Timing Constraints for functional and Test Modes, and Validation.
Run static Low-Power checks on gate level netlists
Verify Logic Equivalency Checks between RTL to Gates and Gates to Gates
Setup signoff Static Timing Analysis and ECO flows and achieve timing closure working with the Design/DFT/PD teams
Timing analysis with sta tools
Constraints debug and sanity checks
Job Description: Experience with Synopsys tools for ASIC Synthesis and Timing Constraints and DFT implementation that includes MBIST and Scan
Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks
Experience with Perl/TCL/Makefile scripting
Experience with full-chip static timing analysis through tapeout, gate level simulations, and Functional ECO implementation with Automated flows
