Experience:
4+ years
Location:
Bangalore
Back end STA with skills on Innovas
3, 5, 7 nm, Prime time
- Experience in STA for block & top level in deep sub-micron tech nodes (TSMC 6nm, 7nm, GF12, TSMC 12nm,....)
- Complex high-speed designs for edge computing applications (3.2 G HBM PHY, Processor hardening for PPA analysis)
- Will need to be hands-on, defining constraints, and margins based on tech nodes, incorporating feedback from the PD Team in the SDC
- Good knowledge of Functional & DFT modes and constraints, Signal integrity, Good knowledge de-rates (OCV, AOCV, POCV)
- Good scripting skills;
experience in Tempus isa plus
