# HCLTech
Undisputed leader in Semiconductor engineering!
# HCLTech
LEADER in Everest Group Semiconductor Engineering Services PEAK Matrix® Assessment 2024!
** 49 years of Product engineering expertise
** 28 years of Silicon design services
** World class team of
4500
engineers
** 250+ tape-outs across multiple foundries/nodes
** Design Services- AMS and Digital Design.
** Approved design partner for major foundries
** Manufacturing Services, Package Design Services, Test Services, Validation Services, Qualification Services.
** One-Stop-Shop for comprehensive Silicon Lifecycle services
JD :
Develop and implement Design for Test (DFT) methodologies for complex hardware systems. Collaborate with design and verification teams to integrate DFT features. Create and validate test plans to ensure thorough coverage and fault detection. Conduct Design for Manufacturing (DFM) analysis and provide recommendations. Support silicon bring-up and debug activities. Automate test processes to enhance efficiency and accuracy. Analyze test data and provide insights for product improvements.
Skills :
Scan insertion
Boundary scan
ATPG (Automatic Test Pattern Generation)
JTAG (Joint Test Action Group)
BIST (Built-In Self-Test) - mbist Verilog/VHDL
Scripting languages (Python, Perl)
DFT tools (tessent, Mentor Graphics DFTAdvisor, Synopsys Tetra MAX)
